
A
ll
and more about Sharp PC-1500
at
http://www.PC-1500.info
RECEIVER
CLOCK
(RC
LO
CK)
:
Cl
oc
k
in
put with a frequen
cy
16 t
im
es
the
de·
si
red receiver shift rate.
TPB
:
,\
pos
it
ive
inJ)U
t
pu
l
se
used
as
a
da
ta l
oad
or reset
st
ro
be.
DATA
AVAI
L
AB
LE(DA)
A l
ow
·le
vcl
vo
ltage at this output ind
ica
tes
tl
tat an entire c
ha
ract
er
has been received and t
rans
fe
rred
to the
Re
ce
i\
•er Holdi
ng
Register.
SERIAL
DATA
IN (SDI):
Serial
data r
-cce
i
ved
on th
is
input
li
ne enters the Recei
ve
r
Sh
ift R
egi
ster at a point detennined by
th
e c
ha
r
ac
ter length. A hi
gh
·
leve
l input volta
ge
mus
t be present
whe
n data is not
be
ing
re
ceived.
CLEAR (C
LEAiR)
:
A l
ow
.l
eve
l vol
tage
at
this input
res
ets
tl
1e I
nt
errupt F
li
p.Flop,
Re
ceiver Holding
Regis
ter, Control
R
egis
ter,
ancl
S
ta
t
us
Re
gister, and sets SERIAL
DATA
OUT
(SDO) hi
gh
.
T
RA
NSMITTER
HO
L
DING
R
EGI
STER
EMPTY
(THRE):
A low.le
ve
l
vo
ltage
at
th
is output indicates that
tl
1e
Transmitter
Hol
di
ng
Regist
er
h
as
t
ra
nsferred its
contents
to
the Tran
sm
itter
Sh
ift
Re
gis
ter and
may
be
re
loa
de
d with a new characte
r.
CH
IP
S
ELEC
T
:I
(CS!):
A
hi
gh·l
eve
l voltage at tllis input
toge
th
er
wit.
h
CS2
and
CS3
se
lects the UART.
REQ
UEST
TO S
END
(RTS):
Tltis
output si
gna
l
te
lls
the peripheral to to
ge
t ready to recei
ve
data. CLEAR TO SE
ND
(C
TS) is
the
res
ponse
from
the pe
ri
pheral. RTS
is
set to a low
·l
e
ve
l
vo
ltage
whe
n data
is
latched in the Tra
ns·
mi
lter
Mo
ld
ing
Re
gister or TR
is
se
t high, and
is
re
set high when both tbe Transrnitter Holding
Register and Transmitter
Shift R
egis
ter a
re
em
pty and
TR
is l
ow
.
SE
RI
AL
DATA
OUT
P
UT
(S
DO
):
The contents of the Transmitter
Sh
i
ft
Reg;s
1er
(start bit, data bits, parity bit, and stop
bi
t(s) are
ser
ia
ll
y shifted out
on
this output.
Wh
en
no
cha
ra
cter is be
ing
transmitted, at high l
evel
is
mai
n·
t
ai
ncd. Start of transmi
ss
ion is defined
as
tlle trans
it
ion
of
the start
bi
t from a
hi
g
h.l
e
vel
to a
low
·
le
vel
oulpul voll
ag
e.
TRA
N
SMITTE
R
BUS
(T B
US
0 · T
BUS
7)
:
T
ra
nsmi
tter pa
ra
llel
data inpu
t.
Th
ese may be externa
ll
y connected to
co
rrespond
in
g
Recei
ve
r
bu
s
1c
nn
i
na
ls
.
RD
/
WR
:
A
low
.
Jcvel
volta
ge
at
this inp
ut
gates data
fr
om
th
e
tra
nsmitter
bu
s to
the
Transmitter
Mo
ldin
g
Re
gi
ster or
the
Con
tr
ol R
egis
ter as chosen
by
registe
r
sele
c
t.
A hi
gh-l
eve
l vohage
ga
t
es
data from
th
e
Re
ce
iver
Holding Register or the S
ta
tu
s Register,
as
chosen by re
gist
er
se
lect, 10 the
rece
i
ve
r
bus.
CH
IP SELE
CT
3
(CS3
)
With hig
h·
levcl
vo
l
ta
ge
at this input together w
it
h
CS
I and
CS2
se
lects the
UA
RT.
PE
R
IPH
E
RA
L ST
AT
US INTERRUPT (
PSI
):
A
hi
gh
·t
O·l
ow
transition on this input line ·sets a bit in the Status Re
gis
ter and cau
ses
an
INT
E
R·
ROPT
(INT
= lo
w}
.
EX
TERNAL ST
AT
US (ES):
A low.J
cvc
l voltage at tllis input sets a bit in the Status R
egi
ster.
C
LEAR
TO
SEND (C
TS
):
When
th
is input from peripheral is hi
gh
,
tr
ansfer of a character
to
the T
ra
nsmitter Shiirt Register
and
shi
f
tin
g
of
se
ri
al
dala on\ is i
nh
ibited.
T
RA
NSM
I
TTE!R
CL
O
CK
(TCLO
CK):
Clock input
wi
th a
fr
equen
cy
16
ti
mes
the
desired transmi
tt
er shift rate.
17
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