Sharp CE-158 Instrukcja Użytkownika Pobierz pdf (Strona 18)

All and more about Sharp PC-1500

at

http:f/www.PC-1500.info

~•rr

-;

TP9

~

~~~~~~~~~~~

~~

~tnsr

_;

;._

tTAS

-:

ASEL

~~~~~~~~~

v-~

~~~

-1

•~~~...,._

~--..,

;,...-~~

~~

II

* READ IS

THE

OVERLAP

OF

CS

!.

CS3. RD/WR • I AND CS2 • 0

Fig. 6 - MODE I

cpu

inte1facc (READ) timing diagram

TABLE 2·1nte

rrupt

Set

and Reset Cond

iti

ons

SET

*

(I

NT =

LOW)

RESET

(INT

=

HIGll

)

CAUSE

CONDITION TIME

DA

Re

ad

of

datn TPB leading edge

(Receipt of dat

a}

THR

E* Read

or

Stntus

or

TPB leading edge

(Ability

to

reload) write

of

chara

cter

THRE

•

TSRE

Read

of

status

or

TPB leading edge

(Transmitter

done)

write

of

character

PSI

Read

of

status

TPB trailing edge

(Negat

ive

edge)

CTS

Read

of

st

:i

t us

TPB leading edge

(Positive

edge wh

en

TH RE ·

TSRE

)

•

Int

err

up

ts will occur only

af

t

er

lhe

1£

b

it

in the Control R

cg

islcr

(se

c Fi

g.

3) has been set.

• TH

RE

will

cause an inter

rupt

on

ly

:a

fter the

TR

bit in

th

e Co

nt

ro

l Register (see Fig. 3) has been

se

t.

FUNCTIONAL DEFI

NIT

IONS FOR CDP1854A

TERMINALS

~

1

0DE

I

SIGNAL: FUNCTION

vDD:

P

os

itive supply voltage

MOD

E

SE

L

ECT

(MODc):

A higll·level voltage

at

this

input

selects

MODE I

operation.

VSS:

Ground

CHIP SELECT 2 (CS2):

A

lo

w·lcvcl voltage at

th

is

input ll>gether with

CS I and

CS

3 selects

th

e COPI 8S4A

UA

RT

.

RECEIVER

BUS

(R BUS 7 · R

BUS

0):

16

Receiver parallel data

outputs

(may

be

ex

·

ternally connected to corresponding tran

smit

·

tcr bus terminals).

INTERRUPT

(IN

T):

A low·lcvel voltage

al

this

output

indicates

the

p1escncc

of

one

of

more

of

the interrupt con·

ditions listed in Table 2.

FR

A

MI

NG

ER

ROR

(FE)

:

A

high-level voltage

at

this

outpu

t indicat

t!S

t

hat

th

e 1eceive

cl

character h

as

no

va

lid st

op

bit, i.e .. the bit fo

ll

ow

ing

th

e paii

ty

bit (if

pr

ogramme

d)

is

no

t a high·levcl volt:tgc. This

ou

tp

ut is

updated

e

ach

li

me

a chnraclcr is

transferred

10

the

Receiver Holding Register.

PARITY

ERROR

or

OVERRUN

ERROR

(PE{OE):

A hig)l·lcvcl voltage

at

this

output

indicat

es

that either

the

PE

or

OE b

it

in the Sll1Us

Register

ha

s been set (see Status Register Bit

Assi

gnme

nt

, Fig.

4)

.

R

EG

ISTER SELECT (RSEL):

Th

is

Input is used to choose either

the

Control

/S

tatlls Register (high input)

or

the

transrnltter{receiver data registers (low

input)

according 10 the

lruth

table

in

Table

I.

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