Sharp mz-800 Instrukcja Obsługi Pobierz pdf (Strona 33)

MZ-800

Pin

name

Pin No.

I/O

Signal

name

Description

00-07

19,20,1 1/0

Z80-CPU Data Bus

Bidirectional, 3-state, Z-80

CPU

bus.

40,39,38

Data and

command

transfer

between

the

Z-80

CPU

and the

3,2

PlO

is carried

out

through

this

data bus.

Do

is

the

least

significant

digit.

B/A

6

I Port B

or

A Select

Port select signal.

Depending

on

the

state

of

this

signal,

the

port

is specified

through

which

data

or

command

is transferred between the

Z-80

CPU

and

the

PlO.

}H

: Port B

L : Port A

CID

5

I Control

or

Date Select

Controlldata

select signal.

Depending

on

the

state

of

this

signal,

control

port

or

data

port

is

selected

for

the

port

assigned

with

B/A.

B/A

CID

Selected

port

L L Port A data

L H Port A

control

H L Port B data

H H Port B

control

et

4 I

Chip

Enable

Chip

enable signal.

A

low

on

this

line enables

the

PlO.

Normally

connected

with

the

1/0 address

decoder

output.

1/1

25 I

System Clock

System clock

CPU

clock

1/1

is

usually

used.

M1

37

I

Machine

Cycle One

Connection

with

CPU M1 signal

(Iow

active).

The

PlO

attains

synchronization

with

the

CPU

interrupt

control

logic

by

M1.

The

PlO

will

be reset

when

M1

is set

low

at

least

for

a

period

of

two

clock cycles

after

turning

iORQ

and

Fm

high

state.

'iORQ

36

I

Input

Output

Request

Connection

with

CPU

iORQ

signal

(Iow

active).

This

signal

perform

data

transfer

between

the

CPU

and the

PlO

in

connection

with

B/A, CID, cr,

and

RD.

If

cr,

RJ), and

iORQ

are

low,

the

data on

the

port

selected

by

B/A are

transferred

to

the

CPU.

If

cr,

iORQ

are

low,

data

or

command

is

written

through

the

port

selected

by

B/A.

Ri)

35 I Read

Connection

with

CPU

RD

signal

(Iow

active).

This

signal

controls

the

direction

of

data

transfer

between

the

CPU

and

the

PlO in

connection

with

B/A, CID,

cr,

and

iORQ.

IEI

24 I

Interrupt

Enable

in

Interrupt

daisy

chain signal.

The

PlO

will

respond

to

the

INTA

cycle

of

the

CPU

only

when

this

signal

is

high.

I--------~--- -

IEO

22

0

Interrupt

Enable

Out

Interrupt

daisy

chain signal.

This

signal is

high

only

when

IEI

is

not

high

with

the

PlO

having

an

interrupt

request. It

goes

low

when

IEI

is

low

or

PlO is

having

an

interrupt

request.

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